The present invention relates to the field of integrated circuits and in particular, to a dual-port memory within a programmable logic integrated circuit.
Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modem programmable logic integrated circuits incorporate programmable logic including logic gates, products terms, or look-up tables. Programmable logic integrated circuits also include embedded user-programmable memory or RAM.
Despite the success of programmable logic, there is a continuing desire to provide greater functionality in a programmable logic integrated circuit, and at the same time, to provide greater flexibility. There is a need to provide higher performance user memories. Specifically, the memories need to be configurable to meet customer demands for FIFOs, CAMs, RAMs, product terms, and ROMs. Also, for greatest flexibility, the memory should be a true dual-port, capable of either reading or writing from both ports at the same time. Read-during-write functionality should be supported. Moreover, the memory ports should be configurable to meet the requirements of the application designed in the programmable logic.
What is needed is a highly flexible memory, which may be configured into a number of different memory function types, and is capable of supporting read-during-write operations.
The present invention provides circuitry and techniques for efficiently and effectively implementing a read-during-write feature for memory blocks. In a specific embodiment, the memory blocks are the dual-port SRAM memory blocks of a programmable logic integrated circuit.
The implementation of the memory cell used in the memory blocks provides good noise immunity by careful selection of the order of devices in write circuits. Routing is simplified, and operation is improved by sharing a word line between read and write circuits. A differential write is provided to improve write times. The placement of a write enable signal also aids in read-during-write functions. A configurable input allows applications in a programmable logic portion of a programmable logic device to select different word lengths.
The memories may be configured as a ROM, RAM, FIFO, CAM, or product terms.
An exemplary embodiment provides a programmable logic integrated circuit. The integrated circuit includes a dual-port memory having a plurality of memory storage cells, each memory storage cell having a memory cell having a first node and a second node. A first series of devices coupled between a first data line and the first node of the memory cell, and a second series of devices coupled between a second data line and the second node of the memory cell are also included. A read cell is coupled to the second node of the memory cell, and a word line is coupled to the gate of a first device in the first series of devices, the gate of a second device in the second series of devices, and the read cell.
Another exemplary embodiment provides a programmable logic integrated circuit. This integrated circuit includes a dual-port memory having a plurality of memory storage cells. Each memory storage cell includes a first device coupled to a first data line, and having a gate coupled to a first word line, a second device coupled between the first device and a first node of a memory cell, and having a gate coupled to a first column select line. A third device coupled to a second node of the memory cell, and having a gate coupled to the first column select line, and a fourth device coupled between the third device and a first complementary data line, and having a gate coupled to the first word line are also included.
Yet a further exemplary embodiment provides a programmable logic integrated circuit having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory coupled to the plurality of logic elements. The memory includes a plurality of memory storage cells, each having a memory cell, a first differential write circuit coupled to memory cell, and selected by a word line, as well as a read cell coupled to the memory cell, and selected by the word line.
A method of writing to a dual-port memory in a programmable logic device consistent with an embodiment of the present invention includes providing a data bit on a data line, and a complement of the data bit on a complementary data line. A read/write word line is selected, thereby activating a first device coupled to the data line, and a second device coupled to the complementary data line. A column select line is selected, thereby activating a third device coupled between the first device and a first node of a memory cell, and a fourth device, coupled between the second device and a second node of the memory cell.
A further embodiment of the present invention provides a programmable logic integrated circuit including a plurality of programmable logic cells, and a dual-port memory coupled to the programmable logic cells. The memory has a plurality of memory cells, each having two write circuits and two read circuits coupled to a storage cell, and arranged in columns and rows, a column decoder, a word line decoder having a plurality of word lines, each word line coupled to one write circuit and one read circuit of each memory cell in a row. A sense amplifier block is also provided, and it includes a plurality of sense amplifiers, each coupled to a column of memory cells. The dual-port memory may be configured as a content addressable memory by bypassing the word line decoder, and providing a comparand input to the plurality of word lines.
Another embodiment provides a method of determining the presence of a match between a data entry and a comparand in a content addressable memory. The memory includes a plurality of memory cells arranged in rows and columns, each memory cell having a write circuit and a read circuit. The write circuit and the read circuit of each memory cell in a row is coupled to one word line, and the read cells of each memory cell in a column are coupled to one first read line and one second read line. The method itself includes writing the data entry to odd numbered memory cells in a column of memory cells, writing a complement of the data entry to even numbered memory cells in the column of memory cells, driving word lines coupled to the even numbered memory cells in the column of memory cells with the comparand, and driving word lines coupled to the odd numbered memory cells in the column of memory cells with a complement of the comparand.
A better understanding of the nature and advantages of the present invention may be gained with reference to the following detailed description and the accompanying drawings.